This course follows the SOC Design course, based on a self-developed IC validation platform (FSIC – Ful-Stack IC). Participants will design an application accelerator and integrating it into SoC, validate it with FPGA and go through IC physical implementation and signoff flow. The course equips participants with the skills and knowledge required to become full-stack IC designers, able to handle all development stages from front-end design, back-end implementation, system debugging and embedded programming. Upon course completion, participants will have the skills and knowledge to tape out SOC chip designs from concept to production. Lectures on Design 1. Introduction to FSIC Architecture. 2. High-level Synthesis using ASIC HLS tool – Catapult. 3. Advanced HLS Topics. 4. Chip design flow. 5. Design for Test 6. Low Power Design. 7. SOC Chip Level Design Components and Issues. 8. Selected topics on high-performance Design 9. Advanced Static Timing Analysis 10. Advanced Verification techniques. Design Flow/Tool 1. Catapult (ASIC HLS) 2. Design Compiler 3. IC Compiler II – Floorplan, Placement, Clock Tree, Routing 4. IC Validator – DRC, LVS 5. PrimeTime – Timing Signoff 6. Optional - DFT and PrimePower Laboratory 1. fisc-sim: FSIC Simulation 2. catapult-hls: Catapult HLS Lab 3. snp-fe: Synopsys Front-end Lab 4. snp-be: Synopsys Back-end Lab 5. hls-ap: Application Accelerator – ASIC Implementation 6. hls-dma: DMA for Application Accelerator – FPGA implementation 7. fsic-fpga – FPGA implementation for Application Accelerator & DMA 8. fsic-final : Final Project with ASIC flow signoff 9. snp-lp : low power design (optional ) 10. snp_dft : design for test ( optional )

Upon completion of the course, students will be able 1. Learn Advanced topics in IC Design, SOC chip-level design 2. Develop an Application Accelerator 3. Complete IC design flow, and be ready for tape out.

Prerequisite e course • EECS course: SOC Design Lab

It expects 5-10 hours week for lab work.