NTU Course
Overview

Vlsi Testing

Offered in 112-2

  • Serial Number

    72463

  • Course Number

    EEE5001

  • Course Identifier

    943 U0010

  • No Class

  • 3 Credits

  • Elective

    GRADUATE INSTITUTE OF ELECTRICAL ENGINEERING / Master Program for Integrated Circuit Design and Automation / PhD Program for Integrated Circuit Design and Automation / GRADUATE INSTITUTE OF ELECTRONICS ENGINEERING

      Elective

    • GRADUATE INSTITUTE OF ELECTRICAL ENGINEERING

    • Master Program for Integrated Circuit Design and Automation

    • PhD Program for Integrated Circuit Design and Automation

    • GRADUATE INSTITUTE OF ELECTRONICS ENGINEERING

  • CHIEN-MO LI
    • View Courses Offered by Instructor

    • COLLEGE OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE GRADUATE INSTITUTE OF ELECTRONICS ENGINEERING

    • cmli@ntu.edu.tw

    • 電機 二館 3 樓 339 室

    • 23635251-339

  • Tue 2, 3, 4

  • 綜401

  • Type 1

  • 42 Student Quota

    NTU 42

  • No Specialization Program

  • English
  • NTU COOL
  • Core Capabilities and Curriculum Planning
  • Notes

    The course is conducted in English。

  • NTU Enrollment Status

    Enrolled
    0/42
    Other Depts
    0/0
    Remaining
    0
    Registered
    0
  • Course Description
    This course introduce basic concepts of VLSI testing. This course will cover both theoretic and practical aspects of testing techniques of VLSI circuits from EDA (electronic design automation) point of view. This is a flipped classroom where students are required to watch video at home and attend the class for discussion. This course requires students to implement a mini EDA tool, automatic test generator (ATPG). This course requires a final team project where students can put together what they learned in the class. The course focuses mainly on digital VLSI circuits.
  • Course Objective
    Students will learn important concepts of VLSI testing knowledge required for both designers and EDA engineers. Students will also learn to implement a EDA tool, automatic test generator (ATPG).
  • Course Requirement
    C++ coding ability. Logic design and VLSI design background.
  • Expected weekly study hours before and/or after class
    Watch on-line video. Study course materials at home
  • Office Hour
  • Designated Reading
    Prof. Li's Video and PPT. https://www.youtube.com/watch?v=nX0XCD0ggHs&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&ab_channel=%E6%9D%8E%E5%BB%BA%E6%A8%A1
  • References
  • Grading
    27%

    Program Assignement

    30%

    Exam

    30%

    Project

    10%

    Classwork

    3%

    Participation

    1. NTU has not set an upper limit on the percentage of A+ grades.
    2. NTU uses a letter grade system for assessment. The grade percentage ranges and the single-subject grade conversion table in the NATIONAL TAIWAN UNIVERSITY Regulations Governing Academic Grading are for reference only. Instructors may adjust the percentage ranges according to the grade definitions. For more information, see the Assessment for Learning Section。
  • Adjustment methods for students
    Adjustment MethodDescription
    A1

    以錄音輔助

    Assisted by recording

    A2

    以錄影輔助

    Assisted by video

  • Make-up Class Information
  • Course Schedule
    Week 01-16introduction, Logic Simulation, Fault Modeling, Fault Simulation, Test Generation, Diagnosis, Built-in Self Test, Test Compression, Memory testing.